The present invention relates in general to field effect transistors, and in particular trench transistors and methods of their manufacture.
FIG. 1 is a simplified cross section of a portion of a conventional metal-oxide-semiconductor field-effect transistor (xe2x80x9cMOSFETxe2x80x9d) trench transistor. A trench 10 is lined with an electrically insulating material 12 that will act as a gate dielectric, and is filled with a conductive material 14, such as polysilicon, which forms the gate. The trench, and hence the gate, extend from the surface of the silicon into the substrate down through a body region 22 (in this case a P-type region) and a drain region 16 (in this case an n-type region). Drain region 16 may be electrically contacted through the substrate of the device. N-type regions on either sides of trench 14 form source terminal 18 of the MOSFET. An active channel region 20 is thus formed along side of trench 16 between source regions 18 and drain region 16.
Trench transistors are often used in power-handling applications, such as power management circuitry for a computer. Trench transistors often operate at 5-100 V, as compared to 2-5 V for a logic-type MOSFET, and trench transistors may control up to 100 amps of current in some applications. Different operating conditions create different problems that must be addressed by proper design of the devices. For example, logic and other low-voltage MOSFETs typically do not have to withstand the voltage differentials that can appear across the terminals of a trench transistor, such as between the gate and drain (xe2x80x9cVGDxe2x80x9d). These high voltages can stress the gate oxide, causing breakdown and degradation leading to device failure.
The gate oxide of a conventional MOSFET is typically formed on a planar surface of a semiconductor wafer. Forming a high-quality oxide layer on a planar surface is relatively simple compared to forming a high-quality oxide layer in a trench for several reasons. One difficulty is that thermally grown oxide will grow faster on a flat surface than at a corner. FIG. 2 is a simplified cross section of a portion of a silicon wafer 30 with a convex corner 32 and a concave corner 34. A layer of thermal oxide 36 is thinner at both the convex corner and at the concave corner. Further, because of higher stress at the silicon-oxide interface at the corners, the corner Sixe2x80x94O bonds are more strained and thus require lower energy to break them. The combination of the thinner oxide and the strained Sixe2x80x94O bonds at the corners make the corner structure less resistant to breakdown at a given electric field across the gate oxide. As a result, the device may exhibit higher leakage currents and suffer related yield and reliability problems. The leakage and other reliability problems are exacerbated by the dry etch process that is typically used to form the trench. Dry etching leaves relatively rough trench walls and creates dangling bonds that further contribute to the leakage.
Thus, it is desirable to produce a trench transistor with a gate dielectric of more uniform thickness, and lower gate leakage current.
The present invention provides a trench metal oxide semiconductor field effect transistor (MOSFET) with a rugged gate dielectric layer which exhibits lower gate leakage current. Gate dielectric (e.g. oxide) is grown on the trench walls and bottom at a temperature sufficiently high to reduce the viscosity of the oxide during growth to result in an oxide layer of more uniform thickness. In one embodiment, the high-temperature oxide layer is grown at 1,100xc2x0 C. to a thickness of about 500 xc3x85 thick and exhibits reduced gate leakage current and higher gate rupture voltage compared to a trench transistor with a gate oxide layer of similar thickness grown at the lower temperatures (e.g., 950xc2x0 C.) conventionally used in the industry. In a preferred embodiment, a gate dielectric layer is made from a first layer of high-temperature gate oxide, a layer of silicon nitride, and a second layer of gate oxide. This composite gate dielectric layer at optimized thicknesses results in even lower gate leakage current and higher gate rupture voltage.
Accordingly, in one embodiment, the present invention provides a field effect transistor formed on a silicon substrate, the transistor including a trench extending into the substrate, the trench having a gate oxide layer having been grown at a temperature above about 1,100xc2x0 C. to result in the gate oxide layer having a thickness that is substantially uniform, the gate oxide layer having substantially uniform stress.
In another embodiment, the present invention provides a field effect transistor formed on a silicon substrate, the transistor including a trench extending into the substrate, the trench being substantially filled by a conductive material that is separated from trench walls and bottom by a dielectric material, the dielectric material including: a silicon nitride layer sandwiched between a first oxide layer adjacent to the trench walls and bottom, and a second oxide layer adjacent to the conductive material, the first oxide layer having a thickness that is substantially greater than that of the second oxide layer.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the trench transistor with rugged gate oxide according to the present invention.